PDP11.JBR[11,DOC] - www.SailDart.orgperm filename PDP11.JBR[11,DOC] blob 
sn#250843 filedate 1976-12-06 generic text, type C, neo UTF8
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C00001 00001
C00002 00002	THIS IS A FILE OF VARIOUS TIDBITS OF SUPPLEMENTARY INFORMATION
C00003 00003	PDP 11/45 PROGRAMMING FEATURES.
C00007 00004	PDP 11/45 SYSTEM HARDWARE FEATURES
C00010 ENDMK
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THIS IS A FILE OF VARIOUS TIDBITS OF SUPPLEMENTARY INFORMATION
ABOUT THE PDP 11/45.  IT INCLUDES CORRECTIONS TO THE VARIOUS
MANUALS AND OTHER GREAT FEATURES THAT HAVE BEEN DISCOVERED.
PEOPLE WHO ARE CONFIDENT THAT THEY HAVE RELEVANT THINGS TO ADD TO
THIS FILE SHOULD FEEL FREE TO DO SO.  IT LIVES ON PDP11.JBR[11,DOC]

					--JBR  1/26/74
PDP 11/45 PROGRAMMING FEATURES.

IT WORKS TO SET PREV MODE TO USER OR SUPERVISOR AND THEN DO A
MFPD R6 TO READ THE USER OR SUPERVISOR R6.	--JBR

THE 11/45 PROCESSOR HANDBOOK LIES AT THE END WHERE IT SAYS (ON P 230)
THAT HALT IN USER MODE TRAPS THROUGH LOCATION 10.  IT REALLY TRAPS
THROUGH LOCATION 4.				--JBR

JMP (Rn)+ AND JSR Rm,(Rn)+ TRANSFER TO THE UNINCREMENTED ADDRESS
						--JBR

The Kernel stack limit register (777774) is really only 8 bits long -
the low 8 bits always read out as zeros.  This means that the stack
limit must be a multiple of 400.
						--BO

It's a lot worse than that!!  Even though the low byte of 777774 is
read as zero, the processor treats it as 377.  So to set up the limit
correctly, you must set it to the high byte - 1 of the lowest stack address.
A yellow stack violation occurs if the high byte of the stack pointer
is exactly equal to the high byte of the stack limit register and the
high 3 bits of the low byte of the stack pointer equals 7.  This means
the stack pointer is within 16 words of C(777774)+400.
A red stack violation occurs if the high byte of the stack pointer is
strictly less than the high byte of the stack limit register or if they
are equal but the high 3 bits of the low byte of the stack pointer
are not 7.  From this comes the restriction that a stack pointer
must not be less than 400 to be violation-free.

The RESET instruction, if attempted in User or Supervisor mode, becomes
a no-op.  A super double bonus!  WAIT, however, does execute if you're
not in Kernel mode.  (They should both be illegal instructions.)
						--BO

The trace trap bit (bit 4, octal 20) of the PSW can NOT be changed by
an explicit write to the PSW, even from the console.  The only things
that can change this bit are

	The console START switch (clears the PSW)
	An interrupt or trap sequence (loads it from the vector)
	The RTI and RTT instructions (load it from the stack).

						--BO
The SPL instruction seems to inhibit ALL interrupts, including trace
traps, for one instruction.  That means that if DDT is one-stepping
it does not see the next instruction after a SPL.

						--BO
PDP 11/45 SYSTEM HARDWARE FEATURES

THE 11/45 STILL DOES BUS ARBITRATION EVEN WHEN IT IS STOPPED SO
THAT YOU CAN STILL HACK IT WITH THE 10/11 INTERFACE WITHOUT 
PUTTING IT INTO A WAIT LOOP.			--JBR

ALL PLACES WHERE THE UNIBUS PLUGS IN MUST HAVE 5V WIRED TO PINS AA2
AND BA2.  THESE ARE THE PINS THAT THE UNIBUS TERMINATOR USES FOR PULLUP.
THE BUS DOES NOT HAVE CONDUCTORS ON THOSE PINS, SO YOU NEED NOT WORRY
ABOUT SHORTING YOUR 5V TO SOMEONE ELSE'S.	--JBR&TAG

The parity control has been modified as follows:  when it has detected
an error and signalled that fact to the CPU, it clears bits 0 and 2
of its control register (777210) (the "enable parity indication" and
"write bad parity" bits).  The reason for this mod is to prevent
getting screwed by parity errors in the trap sequence or the parity
error routine, which would otherwise cause infinite looping.

Bit 19 (PWRFAIL) of the cono word to the 10/11 interface fakes a power fail on
the 11. Useful for when the 11 is halted. Traps thru 24. (beware - it happens
twice!) It works by pulling down on DC LO and AC LO and then releasing. A trap
thru 24 happens at AC LO rising or falling. DC LO coming up causes a bus init.
The bus init feature could be removed by not pulling on DC LO.	pmf

You can't read the processor internal registers from the unibus ( 777772-6 and
others). In particular one can't use the processor interrupt register from
the 10-11 interface. 				pmf


(Current bug - this will be erased when it gets fixed. )
CLR (REG)+ does the clears in the current mode i space not d. It might fail
on other instructions also.			pmf